FIG. 1 illustrates, in block diagram form, an asynchronous Static Random Access Memory (SRAM) 20. SRAM 20 includes Address Buffer 22, Memory Array 24, and Clock Buffer 26. The Write Enable# signal controls the operation of SRAM 20. SRAM 20 responds to the write state (logic low) of the Write Enable # signal by writing the data represented by the Data signal to an address within Memory Array 24 represented by the Address signal. In response to the read state (logic high) of the Write Enable# signal, SRAM 20 reads from Memory Array 24 the data stored at the address represented by the Address signal.
The Joint Electron Device Engineering Council (JEDEC) promulgates standards for semiconductor devices, including SRAM. A JEDEC standard specifies that address hold time, T.sub.AH, must be zero. In other words, an SRAM must support simultaneous transitions of the Write Enable # signal and the Address signal. Usually, the delay of the Address Buffer 22 is such that given simultaneous transitions of both the Write Enable# signal and the Address signal a transition in the Write Clock signal will reach Memory Array 24 before a transition of the X-Address/Y-Address signal. Thus, usually, only the desired operations occur. But this is not always the case, as illustrated by the timing diagram of FIG. 2. At a time t.sub.1 both the Write Enable # signal 13 and the Address signal 15 transition simultaneously. Prior to t.sub.1 these signals represented a command to write data to a first address, Address 1, whereas after t.sub.1 they represent a command to read the data at a second address, Address 2. At time t.sub.2 the X-Address/Y-Address signal 23 transitions from a representation of Address 1 to representation of Address 2; however, the Write Clock signal 29 remains at its active high level, representative of a write command, until t.sub.2. Consequently, for the period between t.sub.2 and t.sub.3, Memory Array 24 writes to Address 2, corrupting the data stored there.
Prior SRAM 30, illustrated in FIG. 3, prevents accidental writes from occurring due to simultaneous transitions of the Write Enable# and Address signals. SRAM 30 does so by inserting a Delay 32 into the address signal, ensuring that transitions of the X-Address/Y-Address signal reach Memory Array 24 after the Write Clock signal, even given simultaneous transitions of the Write Enable# and Address signals. SRAM 30 pays for this certainty with increased access time, defined as the delay from an Address signal transition to when valid data is available from Memory Array 24. In SRAM 30, read access time is approximately the sum of the delay times of Address Buffer 22, Delay 32 and Memory Array 24. Delay 32 may be a small percentage of the total access time, 10% or less, and on the order of a nanosecond; however, such an increase in access time is significant. SRAMs are frequently used to construct secondary microprocessor caches; as such their access times must be compatible with increasing microprocessor clock rates. Thus, a need exists to reduce SRAM access time while preventing accidental writes from occurring due to simultaneous transitions of the Write Enable# and Address signals.